1. Field of the Invention
The present invention relates to a static semiconductor memory device comprising a memory cell using a thin film transistor as a load element.
2. Description of the Related Art
Known memory cells used in a static semiconductor memory device (hereinafter referred to as "SRAM") include, for example, a complete CMOS memory cell utilizing p-channel and n-channel MOS transistors formed in a silicon substrate or in a well region of the silicon substrate as a load transistor and a driving transistor, respectively, and a memory cell using a polycrystalline silicon of a high resistivity as a load element.
A marked increase in the capacity has been achieved nowadays in the memory device comprising a memory cell using a polycrystalline silicon of a high resistivity as a load element. The polycrystalline silicon used in a memory cell of this type has a resistance as high as several tera ohms (10.sup.12 .OMEGA.) in order to keep the current consumption as low as possible during the rest time, i.e., when any of memory cells is not selected. Naturally, the amount of the signal charge supplied to a data memory node within the memory cell is very small. This causes a problem when current leaks from the data memory node through, for example, a PN junction, an insulating film or a transistor. Specifically, the signal charge precharged on the data memory node is more released than that supplied from a load element, that is, data is more liable to be destroyed. Suppose leak current takes place in only one of a large number of memory cells included in a memory device. In this case, the defective memory cell lowers the reliability of the entire memory cell.
Recently, a static memory cell using a thin film transistor (hereinafter referred to as "TFT") as a load element has been developed as a technique capable of solving the above-noted problem inherent in the memory cell using a polycrystalline silicon of a high resistivity as a load element. The TFT is a transistor having the channel region formed in a thin polycrystalline silicon film, not in a silicon substrate. The TFT can be formed in a stacked manner on an ordinary MOS transistor (bulk transistor) having the channel region formed in a silicon substrate. If a TFT is used in place of the p-channel MOS transistor included in a complete CMOS memory cell, the complete CMOS memory cell can be formed with a cell area substantially equal to that of the conventional memory cell using a polycrystalline silicon as a load resistor. In other words, the static memory cell using a TFT as a load element is complete CMOS memory cell. In addition, the memory cell using a TFT permits a high degree of integration like the memory cell using a polycrystalline silicon and also permits a low power consumption and a stable operation like the complete CMOS memory cell.
FIG. 1 is an equivalent circuit diagram showing a static memory cell using a TFT. It is seen that the memory cell comprises two transfer gates consisting of N-channel MOS transistors Q1 and Q2, respectively. A bit line BL is connected to one end of the transistor Q1 (transfer gate), and another bit line /BL to one end of the transistor Q2 (transfer gate). The other ends of these transistors Q1, Q2 are connected to inner memory nodes (data storing nodes) A and B, respectively. Further, the gates of the transistors Q1 and Q2 are commonly connected to a word line WL.
Connected to the inner memory node A are the drain of an N-channel MOS transistor Q3 and the drain of a P-channel TFT Q4. The gates of these transistors Q3 and Q4 are commonly connected to the other inner memory node B. Also connected to the node B are the drain of an N-channel MOS transistor Q5 and the drain of a TFT Q6. The gates of these transistors Q5 and Q6 are commonly connected to the inner memory node A.
The sources of the transistors Q4 and Q6 are connected to a supply node of a power source potential Vcc, with the sources of the transistors Q3 and Q5 being connected to a supply node of a ground potential Vss.
In the memory cell shown in FIG. 1, the transistors Q3 and Q4 form a CMOS inverter. Likewise, transistors Q5 and Q6 form a CMOS inverter. The TFT used as a load element of each of these CMOS inverters functions as a transistor, with the result that current hardly flows to the inner memory node when the TFT is turned off. When the TFT is turned on, however, an oncurrent, which is sufficiently large compared with the memory cell using a load element of a high resistance, flows to the inner memory node.
FIG. 2 shows the relationship between the gate voltage VG (volt) and the drain current ID (ampere) in a typical TFT sized, for example, at 1.5 .mu.m in the channel length, 0.5 .mu.m in the channel width, 25 nm in the thickness of the gate insulation film and 36 nm in the thickness of the polycrystalline silicon layer in which is formed the channel region. The drain voltage is set at -4 V.
As apparent from FIG. 2, the drain current is about 10.sup.-13 (A) when the TFT is turned off, with the gate voltage VG set at 0 V. On the other hand, the drain current is about 10.sup.-7 (A) when the gate voltage is set at -4 V so as to turn the TFT on. It follows that the TFT exhibits an on/off current ratio of about 6 figures, i.e., a resistance ratio of about 6 figures.
On the other hand, each of the inner memory nodes A and B of the memory cell is accompanied by a parasitic capacitance (not shown). The parasitic capacitance tends to be diminished in accordance with the scaling of the memory cell size. However, it is impossible to diminish the parasitic capacitance to a level lower than 10 fF, i.e., 10.sup.-14 F, because of the restrictions such as the resistance to soft error. It follows that the time constant in charging/discharging the inner memory nodes by the on-current of the TFT is about 100 ns (10.sup.-7 A.times.10.sup.-14 F=10.sup.-7 s).
Let us consider a case where the power source potential Vcc supplied to the memory cell is changed in the circuit shown in FIG. 1. In general, such a change in the power source potential is called a power source bump. FIG. 3 shows a change in the potential within the memory cell. A symbol ".tau. 1" shown in the drawing denotes a time constant of the potential Vnod in the case where the inner memory node A or B is charged by the on-current of the TFT. During the period between time t1 and time t2 shown in FIG. 3, the potential difference between the power source potential Vcc and the potential Vnod is greater than the threshold voltage Vth of the P-channel TFT. During this period, the TFT, which should originally be turned off, is also turned on, with the result that this TFT is connected in series to the TFT which is turned from off-state to on-state. It follows that current flows through the N-channel MOS transistor, which is already in an on-state, for a predetermined period of time, i.e., about 100 ns as noted previously. It should be noted that a TFT, which is turned off, is always included in each memory cell. Thus, current of at least 10.sup.-1 A, i.e., 100 mA, flows through the memory cell array when it comes to an SRAM of a large capacity, e.g., at least 4M bits (4.times.10.sup.6 bits). Since the average operating current of the ordinary SRAM is less than 100 mA, the current exceeding 100 mA which flows during the power source bump through an SRAM of 4M bits or more becomes an abnormal current far exceeding the allowable limit.
In general, the power source wiring positions, within the memory cell array for supplying the power source potential to each memory cell is formed of a polycrystalline silicon. A resistance component and a stray capacitance component are included in the power source wiring formed of the polycrystalline silicon. Thus, the power source wiring positioned within the memory cell array can be regarded as a delay line. On the other hand, that portion of the power source wiring for supplying the power source potential to each memory cell which is positioned outside the memory cell array is generally formed of aluminum. Naturally, the power source wiring formed of aluminum is electrically connected within the memory cell array to the power source wiring formed of polycrystalline silicon, which is positioned within the memory cell array. To reiterate, the polycrystalline silicon wiring can be regarded as a delay line. On the other hand, the resistivity of the aluminum wiring is very low. It follows that the time constant of the polycrystalline silicon wiring is diminished with respect to the memory cell positioned closer to the connecting point between the aluminum wiring and the polycrystalline silicon wiring, with the result that a greater DC current flows through said memory cell during the power source bump.